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» Challenges in Physical Chip Design
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ICCD
2004
IEEE
113views Hardware» more  ICCD 2004»
14 years 5 months ago
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
Radu Marculescu, Diana Marculescu, Larry T. Pilegg...
MOBISYS
2007
ACM
13 years 11 months ago
A resource optimized physical movement monitoring scheme for environmental and on-body sensor networks
— Perhaps the most significant challenge in design of on-body sensors is the wearability concern. This concern requires that the size of the nodes (sensors, processing units and ...
Antti Vehkaoja, Mari Zakrzewski, Jukka Lekkala, Sa...
FMICS
2010
Springer
13 years 9 months ago
Model Checking the FlexRay Physical Layer Protocol
Abstract. The FlexRay standard, developed by a cooperation of leading companies in the automotive industry, is a robust communication protocol for distributed components in modern ...
Michael Gerke 0002, Rüdiger Ehlers, Bernd Fin...
TSP
2010
13 years 3 months ago
Improving wireless physical layer security via cooperating relays
Physical (PHY) layer security approaches for wireless communications can prevent eavesdropping without upper layer data encryption. However, they are hampered by wireless channel c...
Lun Dong, Zhu Han, Athina P. Petropulu, H. Vincent...
DAC
2007
ACM
14 years 9 months ago
The KILL Rule for Multicore
Multicore has shown significant performance and power advantages over single cores in commercial systems with a 2-4 cores. Applying a corollary of Moore's Law for multicore, ...
Anant Agarwal, Markus Levy