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» Challenges in Physical Chip Design
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FPL
2009
Springer
107views Hardware» more  FPL 2009»
14 years 1 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
CHI
2006
ACM
14 years 9 months ago
Beyond record and play: backpacks: tangible modulators for kinetic behavior
Digital Manipulatives embed computation in familiar children's toys and provide means for children to design behavior. Some systems use "record and play" as a form ...
Hayes Raffle, Amanda J. Parkes, Hiroshi Ishii, Jos...
ICEIS
2005
IEEE
14 years 2 months ago
Conditions for Interoperability
Abstract: Interoperability for information systems remains a challenge both at the semantic and organisational levels. The original three-level architecture for local databases nee...
B. Nick Rossiter, Michael A. Heather
VEE
2012
ACM
238views Virtualization» more  VEE 2012»
12 years 4 months ago
Swift: a register-based JIT compiler for embedded JVMs
Code quality and compilation speed are two challenges to JIT compilers, while selective compilation is commonly used to tradeoff these two issues. Meanwhile, with more and more Ja...
Yuan Zhang, Min Yang, Bo Zhou, Zhemin Yang, Weihua...
CPHYSICS
2007
106views more  CPHYSICS 2007»
13 years 8 months ago
The way towards thermonuclear fusion simulators
In parallel to the ITER project itself, many initiatives address complementary technological issues relevant to a fusion reactor, as well as many remaining scientific issues. One...
A. Bécoulet, Per Strand, H. Wilson, M. Roma...