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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 3 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ISPASS
2005
IEEE
14 years 2 months ago
BioBench: A Benchmark Suite of Bioinformatics Applications
Recent advances in bioinformatics and the significant increase in computational power available to researchers have made it possible to make better use of the vast amounts of gene...
Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Mano...
WCRE
2002
IEEE
14 years 1 months ago
Estimating Potential Parallelism for Platform Retargeting
Scientific, symbolic, and multimedia applications present diverse computing workloads with different types of inherent parallelism. Tomorrow’s processors will employ varying com...
Linda M. Wills, Tarek M. Taha, Lewis B. Baumstark ...
COMPUTER
2002
103views more  COMPUTER 2002»
13 years 8 months ago
SimpleScalar: An Infrastructure for Computer System Modeling
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...
Todd M. Austin, Eric Larson, Dan Ernst
IPPS
2009
IEEE
14 years 3 months ago
Optimizing assignment of threads to SPEs on the cell BE processor
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...
C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, As...