In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Abstract. This paper derives an optimization-based control methodology for networks of switched and hybrid systems in which each mode is governed by a partial differential equatio...
Alexandre M. Bayen, Robin L. Raffard, Claire Tomli...
We study the role that parallelism plays in time complexariants of Winfree’s abstract Tile Assembly Model (aTAM), a model of molecular algorithmic self-assembly. In the “hiera...
This paper presents Capriccio, a scalable thread package for use with high-concurrency servers. While recent work has advocated event-based systems, we believe that threadbased sy...
J. Robert von Behren, Jeremy Condit, Feng Zhou, Ge...
Abstract. Products within a product family are composed of different component configurations where components have different variable features and a large amount of dependency re...