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HPCA
1996
IEEE
13 years 11 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 7 months ago
Rapid Embedded Hardware/Software System Generation
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya,...
EUROPAR
2000
Springer
13 years 11 months ago
Automatic SIMD Parallelization of Embedded Applications Based on Pattern Recognition
This paper investigates the potential for automatic mapping of typical embedded applications to architectures with multimedia instruction set extensions. For this purpose a (patter...
Rashindra Manniesing, Ireneusz Karkowski, Henk Cor...
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
13 years 11 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
FDL
2007
IEEE
14 years 1 months ago
APDL: A Processor Description Language For Design Space Exploration of Embedded Processors
—This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor design tool sets. The emphasis is on the applicability of the generate...
Nima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, ...