197 search results - page 20 / 40 » Characterizing processor architectures for programmable netw... |
EDO
2006
Springer
13 years 11 months ago
2006
Springer
We present a new publish-subscribe middleware called REDS (REconfigurable Dispatching System) designed to tolerate dynamic reconfigurations of the dispatching infrastructure, like...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Since 2001, there have been a myriad of papers on systematic analysis of Multi-Processor System on Chip (MPSoC) and Network on Chip (NoC). Nevertheless, we only have a few of their...
Lecture Notes
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
EUROPDS
1997
13 years 9 months ago
1997
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...