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IPPS
2006
IEEE
14 years 4 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
ICALP
2005
Springer
14 years 3 months ago
Spatial Logics for Bigraphs
Bigraphs are emerging as a (meta-)model for concurrent calculi, like CCS, ambients, πcalculus, and Petri nets. They are built orthogonally on two structures: a hierarchical place...
Giovanni Conforti, Damiano Macedonio, Vladimiro Sa...
ICALP
2004
Springer
14 years 3 months ago
Group Spreading: A Protocol for Provably Secure Distributed Name Service
In order to enable communication between a dynamic collection of peers with given ID’s, such as “machine.cs.school.edu”, over the Internet, a distributed name service must b...
Baruch Awerbuch, Christian Scheideler
ASAP
1997
IEEE
144views Hardware» more  ASAP 1997»
14 years 2 months ago
Automatic data mapping of signal processing applications
This paper presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applicati...
Corinne Ancourt, Denis Barthou, Christophe Guettie...
FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
14 years 2 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski