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» Chordal Topologies for Interconnection Networks
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GLOBECOM
2006
IEEE
14 years 2 months ago
Link Performance Bounds in Homogeneous Optically Switched Ring Networks
— We consider a ring topology with limited or full switching capability as deployed in high bandwidth metro optical networks and develop a model to estimate the probability of bl...
Shujia Gong, Bijan Jabbari
DAC
1996
ACM
14 years 27 days ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen
IPPS
2003
IEEE
14 years 2 months ago
A Low Cost Fault Tolerant Packet Routing for Parallel Computers
This work presents a new switching mechanism to tolerate arbitrary faults in interconnection networks with a negligible implementation cost. Although our routing technique can be ...
Valentin Puente, José A. Gregorio, Ram&oacu...
IJCAI
1997
13 years 10 months ago
Evolvable Hardware for Generalized Neural Networks
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani...
TSP
2008
116views more  TSP 2008»
13 years 8 months ago
Computation of Delay-Free Nonlinear Digital Filter Networks: Application to Chaotic Circuits and Intracellular Signal Transducti
Abstract--A method for the computation of nonlinear digital filter networks containing delay-free loops is proposed. By preserving the topology of the network this method permits t...
Federico Fontana, Federico Avanzini