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» Chordal Topologies for Interconnection Networks
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ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 2 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
ENTCS
2008
83views more  ENTCS 2008»
13 years 8 months ago
Elastic Flow in an Application Specific Network-on-Chip
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
Daniel Gebhardt, Kenneth S. Stevens
IPCCC
2007
IEEE
14 years 3 months ago
Optimising Networks Against Malware
Rapidly-spreading malicious software is an important threat on today’s computer networks. Most solutions that have been proposed to counter this threat are based on our ability ...
Pierre-Marc Bureau, José M. Fernandez
NOCS
2009
IEEE
14 years 3 months ago
Scalability of network-on-chip communication architecture for 3-D meshes
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuw...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Physical design implementation of segmented buses to reduce communication energy
Abstract— The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, ...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...