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ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
14 years 2 months ago
Silicon neurons that inhibit to synchronize
Abstract—We present a silicon neuron that uses shunting inhibition (conductance-based) with a synaptic rise-time to achieve synchrony. Synaptic rise-time promotes synchrony by de...
John V. Arthur, Kwabena Boahen
CASCON
1994
123views Education» more  CASCON 1994»
13 years 10 months ago
Integrating real-time and partial-order information in event-data displays
The events occurring in the execution of a distributed or parallel application are related by a partial, rather than a total, order. We have developed prototype software that coll...
David J. Taylor, Michael H. Coffin
CASES
2006
ACM
14 years 17 days ago
Probabilistic arithmetic and energy efficient embedded signal processing
Probabilistic arithmetic, where the ith output bit of addition and multiplication is correct with a probability pi, is shown to be a vehicle for realizing extremely energy-efficie...
Jason George, B. Marr, Bilge E. S. Akgul, Krishna ...
IPPS
2007
IEEE
14 years 3 months ago
Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications
Technology trends are such that single event effects (SEE)are likely to become even more of a concern for the future. Decreasing feature sizes, lower operating voltage, and higher...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
IPPS
2010
IEEE
13 years 6 months ago
Scalable multi-pipeline architecture for high performance multi-pattern string matching
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
Weirong Jiang, Yi-Hua Edward Yang, Viktor K. Prasa...