96 search results - page 18 / 20 » Clock-Aware Placement for FPGAs |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
FPGA
2005
ACM
14 years 26 days ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
FPGA
2004
ACM
14 years 22 days ago
2004
ACM
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...