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LCTRTS
1999
Springer
14 years 1 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
ASPLOS
1998
ACM
14 years 29 days ago
Cache-Conscious Data Placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Brad Calder, Chandra Krintz, Simmi John, Todd M. A...
MICRO
1997
IEEE
76views Hardware» more  MICRO 1997»
14 years 28 days ago
A Framework for Balancing Control Flow and Predication
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involve...
David I. August, Wen-mei W. Hwu, Scott A. Mahlke
ICFP
2008
ACM
14 years 8 months ago
Flask: staged functional programming for sensor networks
Severely resource-constrained devices present a confounding challenge to the functional programmer: we are used to having powerful ion facilities at our fingertips, but how can we...
Geoffrey Mainland, Greg Morrisett, Matt Welsh
CASES
2005
ACM
13 years 10 months ago
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Customisable embedded processors are becoming available on the market, thus making it possible for designers to speed up execution of applications by using Application-specific F...
Laura Pozzi, Paolo Ienne