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ASPLOS
2008
ACM
13 years 10 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
ICS
2009
Tsinghua U.
14 years 3 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
APCCAS
2002
IEEE
156views Hardware» more  APCCAS 2002»
14 years 1 months ago
Bit-plane watermarking for zerotree-coded images
In this paper, we develop a robust bit-plane watermarking technique based on zerotree coding. A robust watermark is an imperceptible but indelible code that can be used for owners...
Shih-Hsuan Yang, Hsin-Chang Chen
PLDI
2004
ACM
14 years 2 months ago
Vectorization for SIMD architectures with alignment constraints
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
ICSE
2008
IEEE-ACM
14 years 8 months ago
MontiCore: a framework for the development of textual domain specific languages
In this paper we demonstrate a framework for efficient development of textual domain specific languages and supporting tools. We use a redundance-free and compact definition of le...
Bernhard Rumpe, Hans Grönniger, Holger Krahn,...