966 search results - page 156 / 194 » Code Generation for Embedded Processors |
CGO
2003
IEEE
14 years 2 months ago
2003
IEEE
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
PARELEC
2002
IEEE
14 years 1 months ago
2002
IEEE
Many practical applications generate irregular, nonbalanced divide-and-conquer trees which have different depths, possibly also different numbers of successors at different levels...
HPDC
1996
IEEE
14 years 26 days ago
1996
IEEE
Load balancing involves assigning to each processor, work proportional to its performance, minimizing the execution time of the program. Althoughstatic load balancing can solve ma...
SC
1995
ACM
14 years 7 days ago
1995
ACM
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
ISCAPDCS
2003
13 years 10 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...