Sciweavers

966 search results - page 72 / 194
» Code Generation for Embedded Processors
Sort
View
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
14 years 1 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
SEUS
2008
IEEE
14 years 3 months ago
Model Based Synthesis of Embedded Software
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
Daniel D. Gajski, Samar Abdi, Ines Viskic
CODES
1999
IEEE
14 years 1 months ago
A unified formal model of ISA and FSMD
In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor...
Jianwen Zhu, Daniel Gajski
DAC
2007
ACM
14 years 9 months ago
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
Jia Yu, Jingnan Yao, Jun Yang 0002, Laxmi N. Bhuya...
DAC
2005
ACM
13 years 10 months ago
Smart diagnostics for configurable processor verification
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
Sadik Ezer, Scott Johnson