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» Code Synthesis for Timed Automata
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CODES
2008
IEEE
13 years 9 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
BIRTHDAY
1999
Springer
13 years 11 months ago
Compilation and Synthesis for Real-Time Embedded Controllers
Abstract. This article provides an overview over two constructive approaches to provably correct hard real-time code generation where hard real-time code is generated from abstract...
Martin Fränzle, Markus Müller-Olm
GEOINFORMATICA
2006
86views more  GEOINFORMATICA 2006»
13 years 7 months ago
Decreasing Computational Time of Urban Cellular Automata Through Model Portability
This paper investigates how portability of a model between different computer operating systems can lead to increased efficiency in code execution. The portability problem is not a...
Charles Dietzel, Keith C. Clarke
CBSE
2005
Springer
14 years 1 months ago
Real-Time Scheduling Techniques for Implementation Synthesis from Component-Based Software Models
We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...
Zonghua Gu, Zhimin He
TACAS
2010
Springer
342views Algorithms» more  TACAS 2010»
14 years 2 months ago
SAT Based Bounded Model Checking with Partial Order Semantics for Timed Automata
We study the model checking problem of timed automata based on SAT solving. Our work investigates alternative possibilities for coding the SAT reductions that are based on parallel...
Janusz Malinowski, Peter Niebert