133 search results - page 19 / 27 » Code restructuring for improving cache performance of MPSoCs |
SBCCI
2005
ACM
14 years 2 months ago
2005
ACM
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
ACMMSP
2004
ACM
14 years 2 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
ICMCS
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
EUROPAR
2003
Springer
14 years 1 months ago
2003
Springer
Partial redundancy elimination (PRE) techniques play an important role in optimizing compilers. Many optimizations, such as elimination of redundant expressions, communication opti...
MICRO
1994
IEEE
14 years 21 days ago
1994
IEEE
We examine two pipeline structures which are employed in commercial microprocessors. The first is the load-use interlock (LUI) pipeline, which employs an interlock to ensure corre...