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» Code restructuring for improving cache performance of MPSoCs
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ICS
1999
Tsinghua U.
13 years 11 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
CGO
2008
IEEE
13 years 9 months ago
Comprehensive path-sensitive data-flow analysis
Data-flow analysis is an integral part of any aggressive optimizing compiler. We propose a framework for improving the precision of data-flow analysis in the presence of complex c...
Aditya V. Thakur, R. Govindarajan
ICCS
2005
Springer
14 years 29 days ago
Collecting and Exploiting Cache-Reuse Metrics
Abstract. The increasing gap of processor and main memory performance underlines the need for cache-optimizations, especially on memoryintensive applications. Tools which are able ...
Josef Weidendorfer, Carsten Trinitis
CASES
2008
ACM
13 years 9 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
VECPAR
2000
Springer
13 years 11 months ago
Improving the Performance of Heterogeneous DSMs via Multithreading
This paper analyzes the impact of hardware multithreading support on the performance of distributed shared-memory DSM multiprocessors built out of heterogeneous, single-chip compu...
Renato J. O. Figueiredo, Jeffrey P. Bradford, Jos&...