133 search results - page 9 / 27 » Code restructuring for improving cache performance of MPSoCs |
MICRO
1995
IEEE
13 years 11 months ago
1995
IEEE
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
EMSOFT
2004
Springer
14 years 25 days ago
2004
Springer
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
PLDI
2005
ACM
14 years 1 months ago
2005
ACM
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...
EUROPAR
2003
Springer
14 years 20 days ago
2003
Springer
As compared to a complex single processor based system, on-chip multiprocessors are less complex, more power efficient, and easier to test and validate. In this work, we focus on a...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
The performance of a dynamic optimization system depends heavily on the code it selects to optimize. Many current systems follow the design of HP Dynamo and select a single interp...