11 search results - page 2 / 3 » Combinational Equivalence Checking Using Satisfiability and ... |
APN
2008
Springer
13 years 11 months ago
2008
Springer
Model checking is a powerful and widespread technique for the verification of finite distributed systems. However, the main hindrance for wider application of this technique is the...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
We present an efficient search strategy for satisfiability checking on circuits represented at the register-transfer-level (RTL). We use the RTL circuit structure by extending con...
CORR
2010
Springer
13 years 10 months ago
2010
Springer
We introduce streaming data string transducers that map input data strings to output data strings in a single left-to-right pass in linear time. Data strings are (unbounded) seque...
ECAI
2008
Springer
13 years 11 months ago
2008
Springer
Recent contributions to advancing planning from the classical model to more realistic problems include using temporal logic such as LTL to express desired properties of a solution ...
TCAD
2010
13 years 4 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...