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ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
14 years 2 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ICIAR
2009
Springer
13 years 6 months ago
Score Level Fusion of Ear and Face Local 3D Features for Fast and Expression-Invariant Human Recognition
Abstract. Increasing risks of spoof attacks and other common problems of unimodal biometric systems such as intra-class variations, nonuniversality and noisy data necessitate the u...
Syed M. S. Islam, Mohammed Bennamoun, Ajmal S. Mia...
MASCOTS
1994
13 years 10 months ago
Xmgm: Performance Modeling Using Matrix Geometric Techniques
Over the last two decades a considerable amount of effort has been put in the development and application of matrix geometric techniques for the analysis of queueing systems of wh...
Boudewijn R. Haverkort, Aad P. A. van Moorsel, Dir...
IAJIT
2007
90views more  IAJIT 2007»
13 years 8 months ago
Software Reuse for Mobile Robot Applications Through Analysis Patterns
: Software analysis pattern is an approach of software reuse which provides a way to reuse expertise that can be used across domains at early level of development. Developing softw...
Dayang N. A. Jawawi, Safaai Deris, Rosbi Mamat
CODES
2005
IEEE
14 years 2 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...