10891 search results - page 82 / 2179 » Combining Model Reductions |
124
Voted
WSC
1998
1998
Effective Implementation of Cycle Time Reduction Strategies for Semiconductor Back-end Manufacturing
15 years 4 months ago
Using discrete-event simulation models, a study was conducted to evaluate the current production practices of a high-volume semiconductor back-end operation. The overall goal was ...
111
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ENTCS
2007
15 years 2 months ago
2007
Software model checkers are typically language-specific, require substantial development efforts, and are hard to reuse for other languages. Adding partial order reduction (POR)...
124
Voted
ENTCS
2006
15 years 2 months ago
2006
This paper presents VyrdMC, a runtime verification tool we are building for concurrent software components. The correctness criterion checked by VyrdMC is refinement: Each executi...
112
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VLSID
2007
IEEE
16 years 3 months ago
2007
IEEE
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
149
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PROPERTYTESTING
2010
15 years 15 days ago
2010
We initiate the study of sublinear-time algorithms in the external memory model [Vit01]. In this model, the data is stored in blocks of a certain size B, and the algorithm is char...