5 search results - page 1 / 1 » Common Reusable Verification Environment for BCA and RTL Mod... |
CORR
2007
Springer
13 years 10 months ago
2007
Springer
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
DAC
2007
ACM
14 years 2 months ago
2007
ACM
SoC based system developments commonly employ ESL design ogies and utilize multiple levels of abstract models to provide feasibility study models for architects and development pl...
DAC
1999
ACM
14 years 3 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
DT
2006
13 years 11 months ago
2006
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
CODES
1999
IEEE
14 years 3 months ago
1999
IEEE
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...