415 search results - page 70 / 83 » Comparative evaluation of memory models for chip multiproces... |
SPIN
2010
Springer
13 years 6 months ago
2010
Springer
Directed model checking is a well-established technique to efficiently tackle the state explosion problem when the aim is to find error states in concurrent systems. Although dir...
DANCE
2002
IEEE
14 years 16 days ago
2002
IEEE
Active-network technology envisions deploying execution environments in network elements so that application-specific processing can be applied to network traffic. To provide safe...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...