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    » Comparing Hierarchical Data in External Memory
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    HPCA
    2000
    IEEE
    99views Distributed And Parallel Com...» more  HPCA 2000»
    Register Organization for Media Processing
    13 years 11 months ago
    Register Organization for Media Processing
    Download  cva.stanford.edu
    Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
    Scott Rixner, William J. Dally, Brucek Khailany, P...
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    TVLSI
    2008
    133views more  TVLSI 2008»
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    13 years 6 months ago
    A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
    Download  www.eecs.wsu.edu
    Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
    Mitchell J. Myjak, José G. Delgado-Frias
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    SI3D
    2005
    ACM
    162views Computer Graphics» more  SI3D 2005»
    Texture sprites: texture elements splatted on surfaces
    14 years 17 days ago
    Texture sprites: texture elements splatted on surfaces
    Download  artis.imag.fr
    We present a new interactive method to texture complex geometries at very high resolution, while using little memory and without the need for a global planar parameterization. We ...
    Sylvain Lefebvre, Samuel Hornus, Fabrice Neyret
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    BCS
    2008
    176views Computer Science» more  BCS 2008»
    A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming
    13 years 8 months ago
    A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming
    Download  www.bcs.org
    This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
    Andreas Fidjeland, Wayne Luk, Stephen Muggleton
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    IPPS
    2005
    IEEE
    100views Distributed And Parallel Com...» more  IPPS 2005»
    Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
    14 years 18 days ago
    Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
    Download  liberty.princeton.edu
    Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
    Yun Zhang, Michael Voss
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