Tuning parallel applications requires the use of effective tools for detecting performance bottlenecks. Along a parallel program execution, many individual situations of performan...
The time required to simulate a complete benchmark program using the cycle-accurate model of a microprocessor can be prohibitively high. One of the proposed methodologies, represe...
The two most common strategies for verification and validation, inspection and testing, are in a controlled experiment evaluated in terms of their fault detection capabilities. Th...
Carina Andersson, Thomas Thelin, Per Runeson, Nina...
Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an efficient error detection techniqu...
Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Baba...
We present the design and evaluation of an on-thefly data-race-detection technique that handles applications written for the lazy release consistent (LRC) shared memory model. We ...