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CODES
2006
IEEE
14 years 1 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
MM
2003
ACM
161views Multimedia» more  MM 2003»
14 years 22 days ago
Integrated power management for video streaming to mobile handheld devices
Optimizing user experience for streaming video applications on handheld devices is a significant research challenge. In this paper, we propose an integrated power management appr...
Shivajit Mohapatra, Radu Cornea, Nikil D. Dutt, Al...
EMSOFT
2007
Springer
14 years 1 months ago
Loosely time-triggered architectures based on communication-by-sampling
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
Albert Benveniste, Paul Caspi, Marco Di Natale, Cl...
PVM
2009
Springer
14 years 2 months ago
Hierarchical Collectives in MPICH2
Abstract. Most parallel systems on which MPI is used are now hierarchical: some processors are much closer to others in terms of interconnect performance. One of the most common su...
Hao Zhu, David Goodell, William Gropp, Rajeev Thak...
KDD
2008
ACM
159views Data Mining» more  KDD 2008»
14 years 8 months ago
Semi-supervised learning with data calibration for long-term time series forecasting
Many time series prediction methods have focused on single step or short term prediction problems due to the inherent difficulty in controlling the propagation of errors from one ...
Haibin Cheng, Pang-Ning Tan