622 search results - page 21 / 125 » Comparing the Optimal Performance of Multiprocessor Architec... |
FCCM
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture [3]. The register files consume a s...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is compri...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
IWOMP
2009
Springer
13 years 12 months ago
2009
Springer
Abstract. Exploiting the full computational power of current hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-...