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» Comparing the Optimal Performance of Parallel Architectures
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LCN
2002
IEEE
14 years 8 days ago
A Comparative Throughput Analysis of Scalable Coherent Interface and Myrinet
It has become increasingly popular to construct large parallel computers by connecting many inexpensive nodes built with commercial-off-the-shelf (COTS) parts. These clusters can ...
Sarp Millich, Alan D. George, Sarp Oral
FCCM
2005
IEEE
93views VLSI» more  FCCM 2005»
14 years 1 months ago
Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture
This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture [3]. The register files consume a s...
Zion Kwok, Steven J. E. Wilton
ICPP
1998
IEEE
13 years 11 months ago
Performance Implications of Architectural and Software Techniques on I/O-Intensive Applications
Many large scale applications, have significant I/O requirements as well as computational and memory requirements. Unfortunately, limited number of I/O nodes provided by the conte...
Meenakshi A. Kandaswamy, Mahmut T. Kandemir, Alok ...
MIDDLEWARE
2005
Springer
14 years 26 days ago
Generic Middleware Substrate Through Modelware
Abstract. Conventional middleware architectures suffer from insufficient module-level reusability and the ability to adapt in face of functionality evolution and diversification....
Charles Zhang, Dapeng Gao, Hans-Arno Jacobsen
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
14 years 29 days ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...