1461 search results - page 35 / 293 » Comparing the Optimal Performance of Parallel Architectures |
WSC
1998
13 years 8 months ago
1998
The Time Warp protocol is considered to be an effective synchronization mechanism for parallel discrete event simulation (PDES). However, it is widely recognized that it suffers o...
ICCS
2005
Springer
14 years 28 days ago
2005
Springer
Cray X1 Fortran and C/C++ compilers provide a number of loop transformations, notably vectorization and multistreaming, in order to exploit the multistreaming processor (MSP) hard...
ICPPW
2005
IEEE
14 years 1 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
FPL
2009
Springer
14 years 1 days ago
2009
Springer
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...