118 search results - page 5 / 24 » Compiler Support for Exploiting Coarse-Grained Pipelined Par... |
121
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FCCM
2000
IEEE
15 years 7 months ago
2000
IEEE
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
118
Voted
IPPS
2009
IEEE
15 years 10 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
122
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LCPC
1999
Springer
15 years 7 months ago
1999
Springer
Wavefront computations, characterized by a data dependent flow of computation across a data space, are receiving increasing attention as an important class of parallel computation...
112
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SIGPLAN
2008
15 years 3 months ago
2008
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
196
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SAS
2010
Springer
15 years 1 months ago
2010
Springer
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...