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» Compiler analysis of irregular memory accesses
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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 4 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
PPOPP
2009
ACM
14 years 11 months ago
A compiler-directed data prefetching scheme for chip multiprocessors
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Ka...
TSE
2010
180views more  TSE 2010»
13 years 9 months ago
Aspect-Oriented Race Detection in Java
—In the past, researchers have developed specialized programs to aid programmers in detecting concurrent programming errors such as deadlocks, livelocks, starvation, and data rac...
Eric Bodden, Klaus Havelund