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VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 9 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
COMPSAC
2005
IEEE
14 years 2 months ago
Adaptive Testing, Oracle Generation, and Test Case Ranking for Web Services
Web services and service-oriented architecture are emerging technologies that are changing the way we develop and use computer software. Due to the standardization of web services...
Wei-Tek Tsai, Yinong Chen, Raymond A. Paul, Hai Hu...
CODES
2006
IEEE
14 years 3 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
FCCM
2002
IEEE
174views VLSI» more  FCCM 2002»
14 years 2 months ago
PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs
This paper explores the implications of integrating flexible module generation into a compiler for FPGAs. The objective is to improve the programmabilityof FPGAs, or in other wor...
Oskar Mencer
SEKE
2007
Springer
14 years 3 months ago
A Model-driven Approach to Architecting Secure Software
A software architecture provides a high-level description of a software solution in terms of the structure, topology, and interactions between its principal components. While a nu...
Ebenezer A. Oladimeji, Sam Supakkul, Lawrence Chun...