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ICSE
2007
IEEE-ACM
14 years 7 months ago
Sequential Circuits for Relational Analysis
The Alloy tool-set has been gaining popularity as an alternative to traditional manual testing and checking for design correctness. Alloy uses a first-order relational logic for m...
Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid
POPL
2010
ACM
14 years 5 months ago
A simple, verified validator for software pipelining
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
Jean-Baptiste Tristan, Xavier Leroy
CC
2010
Springer
117views System Software» more  CC 2010»
14 years 2 months ago
Punctual Coalescing
Compilers use register coalescing to avoid generating code for copy instructions. For architectures with register aliasing such as x86, Smith, Ramsey, and Holloway (2004) presented...
Fernando Magno Quintão Pereira, Jens Palsbe...
CGO
2009
IEEE
14 years 2 months ago
ESoftCheck: Removal of Non-vital Checks for Fault Tolerance
—As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. ...
Jing Yu, María Jesús Garzarán...
TPHOL
2009
IEEE
14 years 2 months ago
Practical Tactics for Separation Logic
Abstract. We present a comprehensive set of tactics that make it practical to use separation logic in a proof assistant. These tactics enable the verification of partial correctne...
Andrew McCreight