1198 search results - page 102 / 240 » Compiling for EDGE Architectures |
110
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ICS
2005
Tsinghua U.
15 years 8 months ago
2005
Tsinghua U.
A key step in program optimization is the determination of optimal values for code optimization parameters such as cache tile sizes and loop unrolling factors. One approach, which...
137
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IPPS
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical archit...
125
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IEEEPACT
2000
IEEE
15 years 7 months ago
2000
IEEE
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
156
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LCTRTS
1999
Springer
15 years 7 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
131
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APCSAC
2003
IEEE
15 years 7 months ago
2003
IEEE
Abstract. Increasingly threading has become an important architectural component of programming languages to support parallel programming. Previously we have proposed an elegant la...