1198 search results - page 102 / 240 » Compiling for EDGE Architectures |
ICS
2005
Tsinghua U.
14 years 3 months ago
2005
Tsinghua U.
A key step in program optimization is the determination of optimal values for code optimization parameters such as cache tile sizes and loop unrolling factors. One approach, which...
IPPS
2002
IEEE
14 years 3 months ago
2002
IEEE
This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical archit...
IEEEPACT
2000
IEEE
14 years 2 months ago
2000
IEEE
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
LCTRTS
1999
Springer
14 years 2 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
APCSAC
2003
IEEE
14 years 1 months ago
2003
IEEE
Abstract. Increasingly threading has become an important architectural component of programming languages to support parallel programming. Previously we have proposed an elegant la...