Sciweavers

1198 search results - page 124 / 240
» Compiling for EDGE Architectures
Sort
View
TPHOL
2000
IEEE
15 years 7 months ago
Formal Verification of IA-64 Division Algorithms
The IA-64 architecture defers floating point and integer division to software. To ensure correctness and maximum efficiency, Intel provides a number of recommended algorithms which...
John Harrison
141
Voted
JUCS
2007
107views more  JUCS 2007»
15 years 3 months ago
New Advances in Reconfigurable Computing and its Applications
: In this work we present a survey of different papers about reconfigurable computing and its applications. These papers treat very different reconfigurable-computing applications:...
Miguel A. Vega-Rodríguez, Juan Antonio G&oa...
AROBOTS
2000
93views more  AROBOTS 2000»
15 years 3 months ago
Functional Programming of Behavior-Based Systems
In this paper, I describe a simple functional programming language, GRL, in which most of the characteristic features of the popular behavior-based robot architectures can be conc...
Ian Horswill
153
Voted
CASES
2005
ACM
15 years 5 months ago
An Esterel processor with full preemption support and its worst case reaction time analysis
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...
VEE
2006
ACM
139views Virtualization» more  VEE 2006»
15 years 9 months ago
Vector LLVA: a virtual vector instruction set for media processing
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speci...
Robert L. Bocchino Jr., Vikram S. Adve