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CASES
2005
ACM
15 years 6 months ago
An Esterel processor with full preemption support and its worst case reaction time analysis
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...
VEE
2006
ACM
139views Virtualization» more  VEE 2006»
15 years 10 months ago
Vector LLVA: a virtual vector instruction set for media processing
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speci...
Robert L. Bocchino Jr., Vikram S. Adve
ICSE
2008
IEEE-ACM
16 years 4 months ago
Constructing difference tools for models using the SiDiff framework
Model-driven development requires a full set of development tools. While technologies for constructing graphical editors, compilers etc. are readily available, there is a lack of ...
Maik Schmidt, Tilman Gloetzner
CSSE
2008
IEEE
15 years 10 months ago
Design and Implementation of the Virtual Machine Constructing on Register
: The technology of virtual machines is widely applied in many fields, such as code transplanting, cross-platform computing, and hardware simulation. The main purpose is to simulat...
Weibo Xie, Fu Ting
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
15 years 10 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu