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ICASSP
2008
IEEE
15 years 10 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
WCRE
2002
IEEE
15 years 9 months ago
Analysis of Virtual Method Invocation for Binary Translation
The University of Queensland Binary Translator (UQBT ) is a static binary translation framework that allows for the translation of binary, executable programs, from one architectu...
Jens Tröger, Cristina Cifuentes
IEEEPACT
2000
IEEE
15 years 8 months ago
Instruction Scheduling for Clustered VLIW DSPs
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
Rainer Leupers
HPCA
1997
IEEE
15 years 8 months ago
Datapath Design for a VLIW Video Signal Processor
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S....
ARC
2006
Springer
157views Hardware» more  ARC 2006»
15 years 7 months ago
PISC: Polymorphic Instruction Set Computers
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Won...