Sciweavers

1133 search results - page 25 / 227
» Compiling for Speculative Architectures
Sort
View
ICS
2003
Tsinghua U.
14 years 1 months ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
ASPLOS
2004
ACM
14 years 1 months ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur...
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Fault tolerant nanoelectronic processor architectures
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
FPLE
1995
13 years 12 months ago
Compiler Construction Using Scheme
This paper describes a course in compiler design that focuses on the Scheme implementation of a Scheme compiler that generates native assembly code for a real architecture. The co...
Eric Hilsdale, J. Michael Ashley, R. Kent Dybvig, ...
ICVS
2001
Springer
14 years 26 days ago
Compiling SA-C Programs to FPGAs: Performance Results
Abstract. At the first ICVS, we presented SA-C (“sassy”), a singleassignment variant of the C programming language designed to exploit both coarse-grain and fine-grain parallel...
Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hamm...