931 search results - page 130 / 187 » Compiling for vector-thread architectures |
132
Voted
MICRO
1991
IEEE
15 years 6 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
131
Voted
CASES
2008
ACM
15 years 4 months ago
2008
ACM
fficient Programming Abstractions for Heterogeneous Multicore Systems on Chip Alastair D. Reid Krisztian Flautner Edmund Grimley-Evans ARM Ltd Yuan Lin University of Michigan The ...
137
Voted
CASES
2005
ACM
15 years 4 months ago
2005
ACM
Digital Signal Processing (DSP) is becoming increasingly widespread in portable devices. Due to harsh constraints on power, latency, and throughput in embedded environments, devel...
133
Voted
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
147
Voted
DAC
2007
ACM
16 years 3 months ago
2007
ACM
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...