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» Completeness Results for Memory Logics
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CSL
2008
Springer
13 years 10 months ago
On the Almighty Wand
We investigate decidability, complexity and expressive power issues for (first-order) separation logic with one record field (herein called SL) and its fragments. SL can specify pr...
Rémi Brochenin, Stéphane Demri, &Eac...
EUROMICRO
1998
IEEE
14 years 1 months ago
The Latency Hiding Effectiveness of Decoupled Access/Execute Processors
Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide issue processors due to the increasing penalties that w...
Joan-Manuel Parcerisa, Antonio González
EMSOFT
2006
Springer
14 years 12 days ago
A superblock-based flash translation layer for NAND flash memory
In NAND flash-based storage systems, an intermediate software layer called a flash translation layer (FTL) is usually employed to hide the erase-before-write characteristics of NA...
Jeong-Uk Kang, Heeseung Jo, Jinsoo Kim, Joonwon Le...
MICRO
2006
IEEE
89views Hardware» more  MICRO 2006»
14 years 2 months ago
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
Fernando Castro, Luis Piñuel, Daniel Chaver...
ISCA
1994
IEEE
123views Hardware» more  ISCA 1994»
14 years 26 days ago
Software-Extended Coherent Shared Memory: Performance and Cost
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
David Chaiken, Anant Agarwal