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» Completeness Results for Memory Logics
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FORMATS
2004
Springer
14 years 2 months ago
Model-Checking for Weighted Timed Automata
We study the model-checking problem for weighted timed automata and the weighted CTL logic by the bisimulation approach. Weighted timed automata are timed automata extended with co...
Thomas Brihaye, Véronique Bruyère, J...
CADE
2006
Springer
14 years 9 months ago
Towards Self-verification of HOL Light
The HOL Light prover is based on a logical kernel consisting of about 400 lines of mostly functional OCaml, whose complete formal verification seems to be quite feasible. We would ...
John Harrison
ITC
1996
IEEE
127views Hardware» more  ITC 1996»
14 years 28 days ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey
ICDCS
2000
IEEE
14 years 11 days ago
Graceful Quorum Reconfiguration in a Robust Emulation of Shared Memory
Providing shared-memory abstraction in messagepassing systems often simplifies the development of distributed algorithms and allows for the reuse of sharedmemory algorithms in the...
Burkhard Englert, Alexander A. Shvartsman
TVLSI
2008
150views more  TVLSI 2008»
13 years 8 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz