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» Completeness Results for Memory Logics
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FPGA
2009
ACM
168views FPGA» more  FPGA 2009»
13 years 6 months ago
Large-scale wire-speed packet classification on FPGAs
Multi-field packet classification is a key enabling function of a variety of network applications, such as firewall processing, Quality of Service differentiation, traffic billing...
Weirong Jiang, Viktor K. Prasanna
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
13 years 15 days ago
Hardware synchronization for embedded multi-core processors
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
Christian Stoif, Martin Schoeberl, Benito Liccardi...
ENTCS
2006
134views more  ENTCS 2006»
13 years 8 months ago
Computing Over-Approximations with Bounded Model Checking
Bounded Model Checking (BMC) searches for counterexamples to a property with a bounded length k. If no such counterexample is found, k is increased. This process terminates when ...
Daniel Kroening
TMM
2002
83views more  TMM 2002»
13 years 8 months ago
Systematic evaluation of logical story unit segmentation
Abstract--Although various Logical Story Unit (LSU) segmentation methods based on visual content have been presented in literature, a common ground for comparison is missing. We pr...
Jeroen Vendrig, Marcel Worring
ITC
1997
IEEE
121views Hardware» more  ITC 1997»
14 years 1 months ago
BIST-Based Diagnostics of FPGA Logic Blocks
: Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance....
Charles E. Stroud, Eric Lee, Miron Abramovici