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» Completeness and Decidability in Sequence Logic
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UML
2004
Springer
14 years 22 days ago
SoftContract: Model-Based Design of Error-Checking Code and Property Monitors
This paper discusses a model-based design flow for requirements in distributed embedded software development. Such requirements are specified using a language similar to Linear T...
Luciano Lavagno, Marco Di Natale, Alberto Ferrari,...
CSREAESA
2010
13 years 5 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
SP
2002
IEEE
147views Security Privacy» more  SP 2002»
13 years 7 months ago
CX: A scalable, robust network for parallel computing
CX, a network-based computational exchange, is presented. The system's design integrates variations of ideas from other researchers, such as work stealing, non-blocking tasks...
Peter R. Cappello, Dimitros Mourloukos
CADE
2004
Springer
14 years 7 months ago
The ICS Decision Procedures for Embedded Deduction
contexts such as construction of abstractions, speed may be favored over completeness, so that undecidable theories (e.g., nonlinear integer arithmetic) and those whose decision pr...
Leonardo Mendonça de Moura, Sam Owre, Haral...
ENTCS
2007
178views more  ENTCS 2007»
13 years 7 months ago
Recent Advances in Real-Time Maude
This paper gives an overview of recent advances in Real-Time Maude. Real-Time Maude extends the Maude rewriting logic tool to support formal specification and analysis of object-...
Peter Csaba Ölveczky, José Meseguer