Sciweavers

230 search results - page 28 / 46
» Completing Herbelin's Programme
Sort
View
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
14 years 2 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
ICPP
2008
IEEE
14 years 2 months ago
Implementing and Exploiting Inevitability in Software Transactional Memory
—Transactional Memory (TM) takes responsibility for concurrent, atomic execution of labeled regions of code, freeing the programmer from the need to manage locks. Typical impleme...
Michael F. Spear, Michael Silverman, Luke Dalessan...
IPPS
2008
IEEE
14 years 2 months ago
Model-guided performance tuning of parameter values: A case study with molecular dynamics visualization
In this paper, we consider the interaction between application programmers and tools that automatically search a space of application-level parameters that are believed to impact ...
Yiinju L. Nelson, Bhupesh Bansal, Mary W. Hall, Ai...
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
14 years 2 months ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...