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ISPASS
2010
IEEE
14 years 2 months ago
Visualizing complex dynamics in many-core accelerator architectures
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...
FPL
2005
Springer
98views Hardware» more  FPL 2005»
14 years 1 months ago
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be...
Gareth W. Morris, George A. Constantinides, Peter ...
ICMCS
2000
IEEE
95views Multimedia» more  ICMCS 2000»
14 years 3 days ago
An Extensible Set-Top-Box Architecture for Interactive and Broadcast Services Offering Sophisticated User Guidance
Currently available Set-Top-Boxes (STBs) are mainly used for digital TV reception. The User Interface (UI) and the UI dialog of such a device usually focus on its technological as...
Frank Lonczewski, Rudolf Jaeger
IEEEPACT
2006
IEEE
14 years 1 months ago
Architectural support for operating system-driven CMP cache management
The role of the operating system (OS) in managing shared resources such as CPU time, memory, peripherals, and even energy is well motivated and understood [23]. Unfortunately, one...
Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi
ERSA
2007
194views Hardware» more  ERSA 2007»
13 years 9 months ago
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
Ross Brennan, Michael Manzke, Keith O'Conor, John ...