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» Computational Logic: Memories of the Past and Challenges for...
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IPPS
2008
IEEE
14 years 1 months ago
Lattice Boltzmann simulation optimization on leading multicore platforms
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
Samuel Williams, Jonathan Carter, Leonid Oliker, J...
ERSA
2006
111views Hardware» more  ERSA 2006»
13 years 8 months ago
Promises and Pitfalls of Reconfigurable Supercomputing
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
Maya Gokhale, Christopher Rickett, Justin L. Tripp...
CPHYSICS
2007
106views more  CPHYSICS 2007»
13 years 7 months ago
The way towards thermonuclear fusion simulators
In parallel to the ITER project itself, many initiatives address complementary technological issues relevant to a fusion reactor, as well as many remaining scientific issues. One...
A. Bécoulet, Per Strand, H. Wilson, M. Roma...
CADE
2008
Springer
14 years 7 months ago
Model Stack for the Pervasive Verification of a Microkernel-based Operating System
Abstract. Operating-system verification gains increasing research interest. The complexity of such systems is, however, challenging and many endeavors are limited in some respect: ...
Jan Dörrenbächer, Matthias Daum, Sebasti...
CICC
2011
106views more  CICC 2011»
12 years 7 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....