Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hard...
We describe a software infrastructure designed to support the development of applications that use high-speed networks to connect geographically distributed supercomputers, databa...
Ian T. Foster, Nicholas T. Karonis, Carl Kesselman...
Abstract—The adoption of new hardware and software architectures will make future generations of pervasive devices more flexible and extensible. Networks of computational nodes ...
Alberto Ferrante, Roberto Pompei, Anastasia Stulov...
Network-centric computing aims to solve the problems associated with traditional client/server systems, namely the high performance requirements, and costly maintenance of, the co...
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
Srinivas Chellappa, Franz Franchetti, Markus P&uum...