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    Removing user specified false paths from timing graphs
    15 years 6 months ago
    Removing user specified false paths from timing graphs
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    David Blaauw, Rajendran Panda, Abhijit Das
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    Optimizing sequential verification by retiming transformations
    15 years 6 months ago
    Optimizing sequential verification by retiming transformations
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    Gianpiero Cabodi, Stefano Quer, Fabio Somenzi
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    Efficient building block based RTL code generation from synchronous data flow graphs
    15 years 6 months ago
    Efficient building block based RTL code generation from synchronous data flow graphs
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    Jens Horstmannshoff, Heinrich Meyr
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    Maze routing with buffer insertion and wiresizing
    15 years 6 months ago
    Maze routing with buffer insertion and wiresizing
    Download  nthucad.cs.nthu.edu.tw
    Minghorng Lai, D. F. Wong
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    DAC
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    115views Computer Architecture» more  DAC 2000»
    Projection frameworks for model reduction of weakly nonlinear systems
    15 years 6 months ago
    Projection frameworks for model reduction of weakly nonlinear systems
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    Joel R. Phillips
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