9 search results - page 1 / 2 » Computing Maximal Tiles and Application to Impostor-Based Si... |
CGF
2004
13 years 8 months ago
2004
PCI
2005
Springer
14 years 2 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
SI3D
1997
ACM
14 years 21 days ago
1997
ACM
This paper presents a practical technique to automatically compute approximations of polygonal representations of 3D objects. It is based on a previously developed model simplific...
CF
2009
ACM
14 years 3 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
GECCO
2007
Springer
14 years 2 months ago
2007
Springer
The application of resource-defined fitness sharing (RFS) to shape nesting problems reveals a remarkable ability to discover tilings [7, 8]. These tilings represent exact covers...